Nanomaterials & integration

Nanowires for nanoelectronics & emerging functionnalities

Contact: Bassem Salem

 

The second topic is on the elaboration of Si, Ge and alloyed NWs and their integration in a gate all around device architecture. The elaboration is obtained by the well-known Vapour Liquid Solid method based on the catalytic decomposition of the gaseous precursors on a metallic catalyst droplet (mainly Au). The diameter and the position of the NW are controlled by those of the catalyst. The studies are focused on the elaboration and characterization of heterojunctions by varying the Si/SiGe composition and the doping level through-out the growth. These NWs are then integrated in horizontal or vertical devices with a gate all around architecture to realize MOS-FET and TUN-FET transistors. These devices can be suitable for high performance, low power consumption components and especially for high density integration in integrated circuits (ICs) interconnections regarding to their 3D architecture. Si and SiC NWs potentialities for sensing applications are also explored.