Nanomaterials & integration

Overview

Contact : Dr. Thierry Baron

 

Research activities within this team aim at developing and integrate materials at the nanometer scale in devices to improve Integrate Circuits performances and/or create new functionalities. Miniaturisation of logic and memory devices as well as function diversification through 3D integration is addressed. More exploratory research is also underway on nanomaterials for optoelectronic, sensing and energy fields.

 

The team is actually focused on three main topics.

 

The first one is dedicated to oxide and chacolgenide materials for resistive memories, MOS transistors and MIM capacitors.

Concerning memory applications, we focused on low operating voltage memory with a 3D stacking capability. Chalcogenide (GeS, GeSbTe, GeTe…) and oxide materials (HfO2, TiO2…) based resistive memories offer these potentials. Plasma Enhanced CVD process is developed for the conformal deposition of Phase Change Materials (PCM) such as GeTe and GeSbTe, with specific doping. In situ characterization of the plasma (by Optical Emission Spectroscopy) and the thin film (XPS, via vacuum transfer) are systematically carried out.

MIM capacitors (for DRAM, decoupling applications, RF, VCO, ADC) objective is to obtain high density capacitance (>10 nF/microns²), with a low leakage current (<µA/cm ²) with a constant capacitance. A potential solution is to increase geometrically the electrodes surface by nanostructured capacitors using PEALD for oxide conformal deposition.

Finally, the breakdown mechanisms of gate oxides for MOS transistors (HfSiON/SiON, SiON, SiO2…) are studied by conductive AFM under ultra-high vacuum in cooperation with STMicroelectronics and CEA-Léti.

 

The second topic is on the elaboration of Si, Ge and alloyed NWs and their integration in a gate all around device architecture. The elaboration is obtained by the well-known Vapour Liquid Solid method based on the catalytic decomposition of the gaseous precursors on a metallic catalyst droplet (mainly Au). The diameter and the position of the NW are controlled by those of the catalyst. The studies are focused on the elaboration and characterization of heterojunctions by varying the Si/SiGe composition and the doping level through-out the growth. These NWs are then integrated in horizontal or vertical devices with a gate all around architecture to realize MOS-FET and TUN-FET transistors. These devices can be suitable for high performance, low power consumption components and especially for high density integration in integrated circuits (ICs) interconnections regarding to their 3D architecture. Si and SiC NWs potentialities for sensing applications are also explored.

 

Since one year, a new axis is launched on the development of III-V compounds integration on a Si platform. A 300 mm MOCVD tool is installed, in collaboration with CEA-Leti, in the Leti clean room. We will explore the potentiality of arsenic and phosphorous based compounds epitaxially grown on a Si substrate for nanoelectronic, photonic and photovoltaic applications.

 

Equipments:

  • 200 mm PE-MOCVD deposition of GST materials and 300 mm PE-MOCVD for metal gate
  • Electrical characterization of Resistive-RAM elementary structures
  • Environmental and UHV electrical based-AFM methods
  • 100 mm CVD for Si and Ge NWs shared with CEA-INAC
  • 300 mm MOCVD for III-As and III-P epitaxy
  • 200 mm RTP furnace
  • 200 mm PVD