Fabrication and characterization of Gate-All-Around Field-Effect Transistor based on horizontal GeSn nanowires using “top-down” approach

Team: Nanomaterials & integration

Contact: Dr Bassem SALEM

 

Germanium Tin (Ge1-xSnx or GeSn) alloy material has emerged as a promising candidate for high performance and low-power consumption CMOS devices. By varying the Sn composition, GeSn bandgap can be tuned and low effective mass and high carriers mobility can be achieved. To reach the CMOS market, GeSn technology must surpass silicon performance. On the one hand, a number of process bottlenecks must be overcome, such as the interface quality between the channel and the gateoxide, Fin or nanowires fabrication and source/drain contacts optimization. On the other hand, GeSn multi-gate structures must be realized to improve electrostatic control of the channel.

 

In this context, the position involves the fabrication and the characterization of a Field-Effect- Transistor based on horizontal GeSn nanowires using “top-down” approach. The nanofabrication will be performed at the PTA-LTM/INAC in Grenoble, the GeSn layers on Si substrate will be elaborated by CVD in collaboration with the CEA-Leti and the electrical characterization will be done in collaboration with IMEP-LaHC (Grenoble).

 

Requirements on the candidate:
You hold a PhD in physics or electrical engineering, preferably with a background in solid-state
semiconductor physics. Practical skills in nanotechnology, and knowledge on nanofabrication is highly
welcome.

 

Please send your application by email including a CV, recommendation letter and motivation letter to:

 

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