A FET design for electronic transport studies in graphene nanoribbons

Graphene is a single atomic layer of carbon which exhibits exceptional electronic properties. Electrons in graphene behave as massless Dirac fermions, conferring an extremely high mobility. Despite its amazing properties, graphene is not suitable for logic devices as the bandgap energy in Dirac points is zero. Efforts are focused on converting graphene from semimetal to semiconductor by patterning it down to 10 nm structures, however it represents a challenge from a technological point of view. The LTM studies the materials and fabrication processes that will be used in the future, particularly advanced lithography by self-assembly of block copolymers. This method offers a technological breakthrough to create patterns in the sub-20nm regime on large surfaces. The LTM works on graphene structuration by block copolymers lithography where high quality structures in the sub-10nm regime have been obtained on large surfaces (> 1cm2).


Objectives and detailed work:

The goal of this internship is to fabricate a graphene-nanoribbon-based FET (GNR-FET) in order to study electrical transport in structured graphene. The student will fabricate the GNR-FET devices in the clean room platforms. For this, the student will be trained to use the different technological processes in device fabrication and the characterization techniques involved. At the end, transport measurements will be accomplish to evaluate the electrical performance of GNR-FETs. Career mobility will eventually be improved by doping studies on GNRs. The requested work is essentially experimental, but simulation studies could be considered, depending on first results.


Future possibility:

Ministerial scholarship founding, region or ANR fellowship.

Student profile:

Master 2 in physics or nano. A dynamic and motivated student on high-tech research is strongly recommended, regarding theoretical and experimental aspects in solid state physics.

Position open in:            January 2017                                                    Salary:                   Official internship rates
Duration:                            4 – 6 months

Contacts:                            Marc Zelsmann / Javier Arias

Laboratoire des Technologies de la Microélectronique – CNRS

c/o CEA LETI, 17 rue des Martyrs, 38054, Grenoble
Phone: + 33 4 38 78 92 92

Mail: marc.zelsmann@cea.fr / javier.arias-zapata@cea.fr

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